Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness

We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the genetic algorithm (GA) by reducing the number of active gates used. We accomplish this by combining two ideas: 1) using multiobjective fitness function; 2) evolving circuit layout. It will be shown that using these two approaches allows us to increase the quality of evolved circuits. The circuits are evolved in two phases. Initially the genome fitness in given by the percentage of output bits that are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuits with 100% functionality and minimise the number of active gates in circuit structure. The population is initialised with heterogeneous circuit layouts and the circuit layout is allowed to vary during the evolutionary process. Evolving the circuit layout together with the function is one of the distinctive features of proposed approach. The experimental results show that allowing the circuit layout to be flexible is useful when we want to evolve circuits with the smallest number of gates used. We find that it is better to use a fixed circuit layout when the objective is to achieve the highest number of 100% functional circuits. The two-fitness strategy is most effective when we allow a large number of generations. Evolvable Hardware approach is a recently developed technique to synthesise the electronic circuits using evolutionary algorithms. A central idea of this approach is to represent each possible electronic circuit as chromosome in an evolutionary process in which the standard genetic operators such as initialisation, recombination, selection are carried out. The circuits may be evaluated using software simulation models [1], [2], [3], [4] or alternatively evolved entirely in hardware [5], [6}, [7], [8]. In this paper, we limit our focus to combinational logic circuits, which contain no memory elements. Such circuits contain no feedback paths. Note that this approach can be easily extended for the combinational multiple-valued logic circuits. The approach is an extension of evolvable hardware method proposed in [3], [9], [10], [11] for binary combinational circuits. A similar approach to the design multiple-valued combinational circuit has been discussed in [11], [12], [13]. A discussion concerning a suitable set of logic gates was given in [13]. It has been shown that the GA performance strongly depends on the set of logic gates used to produce the 100% functionally circuits. In [12] experiments were reported which revealed the dependence the GA performance with gate array dimensions and the degree of internal connectivity. Analysis of the evolvable hardware approach for both binary and multiple-valued functions shows us that the GA performance strongly depends on the number of rows and columns and the internal connectivity [9], [12]. In subsequent discussion we define the circuit geometry to mean the layout of the rectangular array of logic cells. It is characterised by just two numbers: the number of rows and columns in the cellular array. The degree of connectivity in the circuit called levels-back defines how many columns of cells to the left of current column can have their outputs connected to the inputs of the current cell, this also applies to the final circuit outputs. This paper presents an extension of the methods discussed above. Here we will discuss two possible ways to improve the quality of evolved circuits. In a previous work the sole objective was to evolve 100% functional circuits. The purpose of our work is to consider this aspect together with attempting to improve the evolved circuits in terms of the number of active gates used. One of the obvious ways to improve it is to use a multi-objective fitness function. Thus in previous works the objective in digital evolution behaviour was to merely produce a 100% functionally correct circuit (F1 fitness). So, the evolutionary process is terminated at this point. Here we continue to evolve the circuit beyond the point of 100% correctness by modifying the fitness function to include a measure of circuit’s efficiency (F2 fitness). As we mention above the choice of suitable circuit geometry is a very complicated task and is intimately linked with the complexity of the function implemented. So, in order to avoid this we investigate the possibility of evolving the circuit geometry at the same time as trying to evolve 100% functional circuits. The circuit geometry defines the length of the chromosome, thus we work with chromosomes of variable length. In this scheme, mutation is carried out in two ways. First, we can mutate genes associated with a circuit in a fixed geometry, and secondly, we can by mutation choose the circuit geometry. The main purpose of circuit layout evolution was to try to evolve the best circuit layout together with evolving circuit functionality. However during the GA execution we find the interesting result that actually using a flexible circuit geometry allows us to reduce the number of active gates in circuit [14], [15]. This was unexpected. In our further research we define several strategies for the GA. We investigate cases where we use homogeneous, heterogeneous or partially heterogeneous (heterogeneous only at the initialisation stage of GA) circuit layouts during GA execution and determine the GA performance as a function of both fitness measures. 1 The Evolutionary Algorithm In order to evolve combinational logic circuits, an evolutionary algorithm using tournament selection with elitism and uniform crossover has been implemented, these details are given in the following subsections. During the evolution process we only allow the circuit layout to be changed by mutation by altering the number of rows or columns. In this case we will refer to this as heterogeneous circuit layout during evolution. When the circuit geometry is not changed during evolution process, we refer to it as the homogeneous circuit layout.